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56.1
date     91.11.05.09.34.55;  author jwh;  state Exp;
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55.1
date     91.08.25.10.13.24;  author jwh;  state Exp;
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54.2
date     91.08.21.14.41.25;  author jwh;  state Exp;
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54.1
date     91.03.18.15.20.38;  author jwh;  state Exp;
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53.1
date     91.03.11.19.22.02;  author jwh;  state Exp;
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52.1
date     91.02.19.09.05.47;  author jwh;  state Exp;
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51.2
date     91.02.10.16.10.21;  author jwh;  state Exp;
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51.1
date     91.01.30.16.04.53;  author jwh;  state Exp;
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1.1
date     91.01.16.15.18.54;  author jwh;  state Exp;
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desc
@Checking in new version 1/16/91 JWH.

@


56.1
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@Automatic bump of revision number for PWS version 3.25
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55.1
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@Automatic bump of revision number for PWS version 3.25A
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54.2
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pws2rcs automatic delta on Wed Aug 21 13:42:03 MDT 1991
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54.1
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@Automatic bump of revision number for PWS version 3.24
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@a0 263
*
*       x_unfl.sa 3.1 12/10/90
*
*       fpsp_unfl --- FPSP handler for underflow exception
*
* Trap disabled results
*       For 881/2 compatibility, sw must denormalize the intermediate
* result, then store the result.  Denormalization is accomplished
* by taking the intermediate result (which is always normalized) and
* shifting the mantissa right while incrementing the exponent until
* it is equal to the denormalized exponent for the destination
* format.  After denormalizatoin, the result is rounded to the
* destination format.
*
* Trap enabled results
*       All trap disabled code applies. In addition the exceptional
* operand needs to made available to the user with a bias of $6000
* added to the exponent.
*

*               Copyright (C) Motorola, Inc. 1990
*                       All Rights Reserved
*
*       THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
*       The copyright notice above does not evidence any
*       actual or intended publication of such source code.



	include fpsp_h

	refr    denorm
	refr    round
	refr    store
	refr    g_rndpr
	refr    g_opcls
	refr    g_dfmtou
	refr    real_unfl
	refr    real_inex
	refr    fpsp_done
	refr    b1238_fix

	def     fpsp_unfl
fpsp_unfl    equ    *
	link            a6,#-LOCAL_SIZE
	fsave           -(a7)
	movem.l         d0-d1/a0-a1,USER_DA(a6)
	fmovem.x        fp0-fp3,USER_FP0(a6)
	fmovem.l        FPCONTROL/FPSTATUS/FPIADDR,USER_FPCONTROL(a6)
*
	bsr.l           unf_res ;denormalize, round & store interm op
*
* If underflow exceptions are not enabled, check for inexact
* exception
*
	btst            #unfl_bit,FPCONTROL_ENABLE(a6)
	beq.b           ck_inex

	btst            #E3,E_BYTE(a6)
	beq.b           no_e3_1
*
* Clear dirty bit on dest resister in the frame before branching
* to b1238_fix.
*
	bfextu          CMDREG3B(a6){6:3},d0    ;get dest reg no
	bclr            d0,FPR_DIRTY_BITS(a6)   ;clr dest dirty bit
	bsr.l           b1238_fix               ;test for bug1238 case
	move.l          USER_FPSTATUS(a6),FPSTATUS_SHADOW(a6)
	ori.l           #sx_mask,E_BYTE(a6)
no_e3_1    equ    *
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	frestore        (a7)+
	unlk            a6
	bra.l           real_unfl
*
* It is possible to have either inex2 or inex1 exceptions with the
* unfl.  If the inex enable bit is set in the FPCONTROL, and either
* inex2 or inex1 occured, we must clean up and branch to the
* real inex handler.
*
ck_inex    equ    *
	move.b          FPCONTROL_ENABLE(a6),d0
	and.b           FPSTATUS_EXCEPT(a6),d0
	andi.b          #$3,d0
	beq.b           unfl_done

*
* Inexact enabled and reported, and we must take an inexact exception
*
take_inex    equ    *
	btst            #E3,E_BYTE(a6)
	beq.b           no_e3_2
*
* Clear dirty bit on dest resister in the frame before branching
* to b1238_fix.
*
	bfextu          CMDREG3B(a6){6:3},d0    ;get dest reg no
	bclr            d0,FPR_DIRTY_BITS(a6)   ;clr dest dirty bit
	bsr.l           b1238_fix               ;test for bug1238 case
	move.l          USER_FPSTATUS(a6),FPSTATUS_SHADOW(a6)
	ori.l           #sx_mask,E_BYTE(a6)
no_e3_2    equ    *
	move.b          #INEX_VEC,EXC_VEC+1(a6)
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	frestore        (a7)+
	unlk            a6
	bra.l           real_inex

unfl_done    equ    *
	bclr            #E3,E_BYTE(a6)
	beq.b           e1_set          ;if set then branch
*
* Clear dirty bit on dest resister in the frame before branching
* to b1238_fix.
*
	bfextu          CMDREG3B(a6){6:3},d0            ;get dest reg no
	bclr            d0,FPR_DIRTY_BITS(a6)   ;clr dest dirty bit
	bsr.l           b1238_fix               ;test for bug1238 case
	move.l          USER_FPSTATUS(a6),FPSTATUS_SHADOW(a6)
	ori.l           #sx_mask,E_BYTE(a6)
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	frestore        (a7)+
	unlk            a6
	bra.l           fpsp_done
e1_set    equ    *
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	unlk            a6
	bra.l           fpsp_done
*
*       unf_res --- underflow result calculation
*
unf_res    equ    *
	bsr.l           g_rndpr         ;returns RND_PREC in d0 0=ext,
*                                       ;1=sgl, 2=dbl
*                                       ;we need the RND_PREC in the
*                                       ;upper word for round
	move.w          #0,-(a7)
	move.w          d0,-(a7)        ;copy RND_PREC to stack
*
*
* If the exception bit set is E3, the exceptional operand from the
* fpu is in WBTEMP; else it is in FPTEMP.
*
	btst            #E3,E_BYTE(a6)
	beq.b           unf_E1
unf_E3    equ    *
	lea             WBTEMP(a6),a0   ;a0 now points to operand
*
* Test for fsgldiv and fsglmul.  If the inst was one of these, then
* force the precision to extended for the denorm routine.  Use
* the user's precision for the round routine.
*
	move.w          CMDREG3B(a6),d1 ;check for fsgldiv or fsglmul
	andi.w          #$7f,d1
	cmpi.w          #$30,d1         ;check for sgldiv
	beq.b           unf_sgl
	cmpi.w          #$33,d1         ;check for sglmul
	bne.b           unf_cont        ;if not, use FPCONTROL prec in round
unf_sgl    equ    *
	clr.l           d0
	move.w          #$1,(a7)        ;override g_rndpr precision
*                                       ;force single
	bra.b           unf_cont
unf_E1    equ    *
	lea             FPTEMP(a6),a0   ;a0 now points to operand
unf_cont    equ    *
	bclr            #sign_bit,LOCAL_EX(a0)  ;clear sign bit
	sne             LOCAL_SGN(a0)           ;store sign

	bsr.l           denorm          ;returns denorm, a0 points to it
*
* WARNING:
*                               ;d0 has guard,round sticky bit
*                               ;make sure that it is not corrupted
*                               ;before it reaches the round subroutine
*                               ;also ensure that a0 isn't corrupted

*
* Set up d1 for round subroutine d1 contains the PREC/MODE
* information respectively on upper/lower register halves.
*
	bfextu          FPCONTROL_MODE(a6){2:2},d1      ;get mode from FPCONTROL
*                                               ;mode in lower d1
	add.l           (a7)+,d1                ;merge PREC/MODE
*
* WARNING: a0 and d0 are assumed to be intact between the denorm and
* round subroutines. All code between these two subroutines
* must not corrupt a0 and d0.
*
*
* Perform Round
*       Input:          a0 points to input operand
*                       d0{31:29} has guard, round, sticky
*                       d1{01:00} has rounding mode
*                       d1{17:16} has rounding precision
*       Output:         a0 points to rounded operand
*

	bsr.l           round           ;returns rounded denorm at (a0)
*
* Differentiate between store to memory vs. store to register
*
unf_store    equ    *
	bsr.l           g_opcls         ;returns opclass in d0{2:0}
	cmpi.b          #$3,d0
	bne.b           not_opc011
*
* At this point, a store to memory is pending
*
opc011    equ    *
	bsr.l           g_dfmtou
	tst.b           d0
	beq.b           ext_opc011      ;If extended, do not subtract
*                               ;If destination format is sgl/dbl,
	subq.w          #1,LOCAL_EX(a0) ;account for denorm bias vs.
*                               ;normalized bias
*                               ;          normalized   denormalized
*                               ;single       $7f           $7e
*                               ;double       $3ff          $3fe
*
ext_opc011    equ    *
	bsr.l           store           ;stores to memory
	bra.b           unf_done        ;finish up

*
* At this point, a store to a float register is pending
*
not_opc011    equ    *
	bsr.l           store   ;stores to float register
*                               ;a0 is not corrupted on a store to a
*                               ;float register.
*
* Set the condition codes according to result
*
	tst.l           LOCAL_HI(a0)    ;check upper mantissa
	bne.b           ck_sgn
	tst.l           LOCAL_LO(a0)    ;check lower mantissa
	bne.b           ck_sgn
	bset            #z_bit,FPSTATUS_CC(a6) ;set condition codes if zero
ck_sgn    equ    *
	btst            #sign_bit,LOCAL_EX(a0)  ;check the sign bit
	beq.b           unf_done
	bset            #neg_bit,FPSTATUS_CC(a6)

*
* Finish.
*
unf_done    equ    *
	btst            #inex2_bit,FPSTATUS_EXCEPT(a6)
	beq.b           no_aunfl
	bset            #aunfl_bit,FPSTATUS_AEXCEPT(a6)
no_aunfl    equ    *
	rts

	end
@


53.1
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@Automatic bump of revision number for PWS version 3.24B
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52.1
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@Automatic bump of revision number for PWS version 3.24A
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51.1
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	include fpsp.h
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1.1
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@Initial revision
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