head     56.3;
access   paws bayes jws quist brad dew jwh;
symbols  ;
locks    ; strict;
comment  @# @;


56.3
date     93.01.27.13.33.33;  author jwh;  state Exp;
branches ;
next     56.2;

56.2
date     93.01.27.12.10.01;  author jwh;  state Exp;
branches ;
next     56.1;

56.1
date     91.11.05.09.31.26;  author jwh;  state Exp;
branches ;
next     55.1;

55.1
date     91.08.25.10.09.30;  author jwh;  state Exp;
branches ;
next     54.1;

54.1
date     91.03.18.15.17.16;  author jwh;  state Exp;
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next     53.1;

53.1
date     91.03.11.19.17.46;  author jwh;  state Exp;
branches ;
next     52.1;

52.1
date     91.02.19.09.02.57;  author jwh;  state Exp;
branches ;
next     51.1;

51.1
date     91.01.30.16.02.09;  author jwh;  state Exp;
branches ;
next     50.1;

50.1
date     90.10.29.16.15.43;  author jwh;  state Exp;
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next     49.1;

49.1
date     90.08.14.14.04.03;  author jwh;  state Exp;
branches ;
next     48.1;

48.1
date     90.07.26.11.09.47;  author jwh;  state Exp;
branches ;
next     47.1;

47.1
date     90.05.14.10.47.45;  author dew;  state Exp;
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next     46.1;

46.1
date     90.05.07.08.35.44;  author jwh;  state Exp;
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next     45.1;

45.1
date     90.04.19.15.42.37;  author jwh;  state Exp;
branches ;
next     44.1;

44.1
date     90.04.01.22.00.32;  author jwh;  state Exp;
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next     43.1;

43.1
date     90.03.20.13.50.25;  author jwh;  state Exp;
branches ;
next     42.1;

42.1
date     90.01.23.17.35.57;  author jwh;  state Exp;
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next     41.1;

41.1
date     89.12.22.11.18.05;  author jwh;  state Exp;
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next     40.1;

40.1
date     89.09.29.11.41.01;  author jwh;  state Exp;
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next     39.1;

39.1
date     89.09.26.16.26.26;  author dew;  state Exp;
branches ;
next     38.1;

38.1
date     89.08.29.11.16.53;  author jwh;  state Exp;
branches ;
next     37.1;

37.1
date     89.05.12.11.30.14;  author dew;  state Exp;
branches ;
next     36.1;

36.1
date     89.02.06.10.09.13;  author dew;  state Exp;
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next     35.1;

35.1
date     89.02.02.13.20.44;  author dew;  state Exp;
branches ;
next     34.1;

34.1
date     89.01.23.15.56.00;  author jwh;  state Exp;
branches ;
next     33.1;

33.1
date     89.01.16.11.31.12;  author dew;  state Exp;
branches ;
next     32.1;

32.1
date     89.01.10.11.37.18;  author bayes;  state Exp;
branches ;
next     31.1;

31.1
date     88.12.14.17.58.14;  author bayes;  state Exp;
branches ;
next     30.1;

30.1
date     88.12.09.13.36.32;  author dew;  state Exp;
branches ;
next     29.1;

29.1
date     88.10.31.15.20.33;  author bayes;  state Exp;
branches ;
next     28.1;

28.1
date     88.10.06.10.49.58;  author dew;  state Exp;
branches ;
next     27.1;

27.1
date     88.09.29.11.15.46;  author bayes;  state Exp;
branches ;
next     26.1;

26.1
date     88.09.28.12.33.38;  author bayes;  state Exp;
branches ;
next     25.1;

25.1
date     88.03.02.09.10.15;  author bayes;  state Exp;
branches ;
next     24.1;

24.1
date     87.08.31.09.20.45;  author jws;  state Exp;
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next     23.1;

23.1
date     87.08.26.09.57.14;  author bayes;  state Exp;
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next     22.1;

22.1
date     87.08.17.10.37.50;  author bayes;  state Exp;
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next     21.1;

21.1
date     87.08.12.13.25.22;  author bayes;  state Exp;
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next     20.1;

20.1
date     87.07.30.10.35.56;  author bayes;  state Exp;
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next     19.1;

19.1
date     87.06.01.07.54.17;  author jws;  state Exp;
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next     18.1;

18.1
date     87.05.20.14.48.44;  author bayes;  state Exp;
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next     17.1;

17.1
date     87.04.30.10.06.25;  author jws;  state Exp;
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next     16.1;

16.1
date     87.04.26.15.20.45;  author jws;  state Exp;
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next     15.1;

15.1
date     87.04.13.08.47.01;  author jws;  state Exp;
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next     14.1;

14.1
date     87.04.01.14.43.43;  author jws;  state Exp;
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next     13.1;

13.1
date     87.02.28.18.08.46;  author jws;  state Exp;
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next     12.1;

12.1
date     87.02.02.12.55.26;  author jws;  state Exp;
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next     11.1;

11.1
date     87.01.19.09.22.04;  author jws;  state Exp;
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next     10.1;

10.1
date     86.12.24.10.28.12;  author jws;  state Exp;
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next     9.2;

9.2
date     86.12.18.14.35.19;  author jws;  state Exp;
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next     9.1;

9.1
date     86.12.12.13.51.18;  author bayes;  state Exp;
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next     8.1;

8.1
date     86.11.27.11.25.45;  author jws;  state Exp;
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next     7.1;

7.1
date     86.11.20.13.12.55;  author hal;  state Exp;
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next     6.1;

6.1
date     86.11.04.17.14.33;  author paws;  state Exp;
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next     5.1;

5.1
date     86.10.28.16.02.46;  author hal;  state Exp;
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next     4.1;

4.1
date     86.09.30.19.15.39;  author hal;  state Exp;
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next     3.2;

3.2
date     86.09.24.09.58.27;  author hal;  state Exp;
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next     3.1;

3.1
date     86.09.01.11.27.30;  author hal;  state Exp;
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next     2.1;

2.1
date     86.07.30.14.18.44;  author hal;  state Exp;
branches ;
next     1.1;

1.1
date     86.06.30.13.44.05;  author danm;  state tmp;
branches ;
next     ;


desc
@Base file for PWS 3.2 release.

@


56.3
log
@
pws2rcs automatic delta on Wed Jan 27 13:14:25 MST 1993
@
text
@			     { file MC68881 }
import
  sysglobals, codegen, assemble, genutils, genexprmod;

implement

  var
    rmask,fregloc : attrtype;
    fregcount: shortint;

  procedure NIL_attributes(fexp: exptr);
    { Called as part of the $FLOAT TEST$ option }
    var
      ptr: elistptr;
    begin
    with fexp^ do
      begin
      attr := NIL;
      case eclass of
	eqnode, nenode, ltnode, lenode, gtnode, genode, innode, subsetnode,
	supersetnode, unionnode, diffnode, intersectnode, concatnode,
	addnode, subnode, mulnode, divnode, modnode, shftnode, ornode, andnode:
	  begin
	  NIL_attributes(opnd1);
	  NIL_attributes(opnd2);
	  end;
	negnode, notnode, floatnode, derfnode, succnode,
	bufnode, absnode, chrnode, oddnode, ordnode,
	prednode, strlennode, strmaxnode, roundnode, sqrnode, truncnode:
	  NIL_attributes(opnd);
	subscrnode:
	  begin
	  NIL_attributes(arayp);
	  NIL_attributes(indxp);
	  end;
	substrnode:
	  begin
	  NIL_attributes(arayp);
	  NIL_attributes(indxp);
	  NIL_attributes(lengthp);
	  end;
	selnnode:
	  NIL_attributes(recptr);
	fcallnode:
	  begin
	  ptr := actualp;
	  while ptr <> NIL do
	    begin
	    NIL_attributes(ptr^.expptr);
	    ptr := ptr^.nextptr;
	    end;
	  end;
	setdenonode:
	  begin
	  ptr := setvarpart;
	  while ptr <> NIL do
	    begin
	    NIL_attributes(ptr^.lowptr);
	    NIL_attributes(ptr^.hiptr);
	    ptr := ptr^.nextptr;
	    end;
	  end;
	otherwise { Terminal node }
      end; { case }
      end; { with }
    end; { NIL_attributes }


  procedure makerealaddressable( fexp : exptr );
	{ Make operand addressable while handling float node }
    begin
	  force_unpack := true;
	  makeaddressable(fexp);
	  force_unpack := false;
	  with fexp^.attr^ do
	    if ((storage = bytte) or (storage = wrd)) and not signbit then
	      extend(fexp,succ(storage));
    end;


  procedure loadrealvalue(fexp: exptr);
    { Load 64 bit real into a floating point register }
    var
      op : attrtype;
    begin
    makerealaddressable(fexp);
    if fexp^.attr^.addrmode <> inFreg then
      begin
      with op do
	begin
	regnum := getreg(F);
	addrmode := inFreg;
	storage := multi;
	end;
      with fexp^ do
	begin
	with attr^ do
	  if ((storage = bytte) or (storage = wrd)) and not signbit then
	    extend(fexp,succ(storage));
	freeregs(attr);
	emit2(fmove,attr^,op);
	attr^.storage := multi;
	attr^.addrmode := inFreg;
	attr^.regnum := op.regnum;
	end; { with fexp^ }
      end;
    end;

  procedure pushrealvalue(fexp: exptr);
    { Addrmode is inFreg.  Move the 64 bit
      real number onto the stack. }
    begin
    makerealaddressable(fexp);
    SPminus.storage := multi;
    emit2(fmove,fexp^.attr^,SPminus);
    freeregs(fexp^.attr);
    fexp^.attr^.addrmode := topofstack;
    end;

  procedure pushrealaddress(fexp: exptr);
    { Addrmode is inFreg. Move to a temporary.
      Push the address of the temporary.}
    var
      op: attrtype;
    begin
    makerealaddressable(fexp);
    getlocstorage(8,op);
    op.storage := multi;
    emit2(fmove,fexp^.attr^,op);
    emit1(pea,op);
    freeregs(fexp^.attr);
    end;

  procedure moverealvalue(fexp: exptr; var at: attrtype);
    { Addrmode is inFreg.  Move 64 bit real from
      the floating point registers to the address in at. }
    var
      op: attrtype;
    begin
    makerealaddressable(fexp);
    emit2(fmove,fexp^.attr^,at);
    freeregs(fexp^.attr);
    end;

  procedure saverealregs;
    var
      rn: regrange;

    begin
    with rmask do
      begin
      addrmode := fmultiple;
      fregcount := 0;
      for rn := 0 to maxreg do
	if reg[F,rn].allocstate = allocated then
	  begin
	  fregcount := fregcount + 1;
	  fregs[rn] := true;
	  end
	else
	  fregs[rn] := false;

      if fregcount > 0 then
	begin
	getlocstorage(fregcount*12,fregloc);
	emit2(fmovem,rmask,fregloc);  { Save registers in temporary storage }
	end;
      end;
    end;

  procedure reloadrealregs;

    begin
    if fregcount > 0 then
      emit2(fmovem,fregloc,rmask); { Restore registers from temporary storage }
    end;

  procedure realop(fexp: exptr);
    var
      op1,op2: attrtype;
      valp : csp;
    begin
    with fexp^, attr^ do
      case eclass of
	fcallnode:
	  with fptr^, actualp^ do
	    begin
	    if {actualp^.}expptr^.eclass = floatnode then
	      begin
	      makerealaddressable({actualp^.}expptr^.opnd);
	      getattrec({actualp^.}expptr);
	      liftattr({actualp^.}expptr,{actualp^.}expptr^.opnd);
	      {actualp^.}expptr^.attr^.storage :=
					{actualp^.}expptr^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable({actualp^.}expptr);
	    if spkey <> spln then
	      if {actualp^.}expptr^.attr^.addrmode = inFreg then
		with op1 do
		  begin
		  addrmode := inFreg;
		  regnum := {actualp^.}expptr^.attr^.regnum;
		  end
	      else
		begin
		freeregs({actualp^.}expptr^.attr);
		with op1 do
		  begin
		  addrmode := inFreg;
		  regnum := getreg(F);
		  end;
	      end;
	    case spkey of
	      spsin:    emit2(fsin,{actualp^.}expptr^.attr^,op1);
	      spcos:    emit2(fcos,{actualp^.}expptr^.attr^,op1);
	      spsqrt:   emit2(fsqrt,{actualp^.}expptr^.attr^,op1);
	      spexp:    emit2(fetox,{actualp^.}expptr^.attr^,op1);
	      sparctan: emit2(fatan,{actualp^.}expptr^.attr^,op1);
	      spln:
		begin
		loadrealvalue(expptr);
		new(valp);
		with valp^ do
		  begin
		  cclass := reel;
		  rval := 0.5;
		  end;
		with op1 do
		  begin
		  addrmode := labelledconst;
		  valp := poolit(valp);
		  constvalp := valp;
		  storage := multi;
		  offset := 0;
		  end;
		emit2(fcmp,op1,expptr^.attr^);
		op1.offset := 14;
		emit1(fblt,op1);
		with op1 do
		  begin
		  addrmode := immediate;
		  smallval := 1;
		  storage := wrd;
		  end;
		emit2(fsub,op1,expptr^.attr^);
		emit2(flognp1,expptr^.attr^,expptr^.attr^);
		op1.offset := 4;
		op1.storage := bytte;
		emit1(bra,op1);
		emit2(flogn,expptr^.attr^,expptr^.attr^);
		op1.regnum := expptr^.attr^.regnum;
		end;
	      end;
	    addrmode := inFreg;
	    regnum := op1.regnum;
	    storage := multi;
	    signbit := true;
	    end;
	negnode,absnode:   { 64 bit }
	  begin
	  makerealaddressable(opnd);
	  freeregs(opnd^.attr);
	  with op1 do
	    begin
	    addrmode := inFreg;
	    regnum := getreg(F);
	    end;
	  if eclass = negnode then
	    emit2(fneg,opnd^.attr^,op1)
	  else
	    emit2(fabs,opnd^.attr^,op1);
	  addrmode := inFreg;
	  regnum := op1.regnum;
	  storage := multi;
	  signbit := true;
	  end;
	sqrnode:
	  begin
	  loadrealvalue(opnd);
	  emit2(fmul,opnd^.attr^,opnd^.attr^);
	  liftattr(fexp,opnd);
	  end;
	floatnode: { int to 64 bit }
	  begin
	  loadrealvalue(opnd);
	  liftattr(fexp,opnd);
	  end;
	subnode, divnode: { 64 bit }
	  begin
	  { Evaluate a complicated operand first }
	  if opnd1^.num_ops >= opnd2^.num_ops then
	    begin
	    loadrealvalue(opnd1);
	    if opnd2^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd2^.opnd);
	      getattrec(opnd2);
	      liftattr(opnd2,opnd2^.opnd);
	      opnd2^.attr^.storage := opnd2^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd2);
	    end
	  else
	    begin
	    if opnd2^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd2^.opnd);
	      getattrec(opnd2);
	      liftattr(opnd2,opnd2^.opnd);
	      opnd2^.attr^.storage := opnd2^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd2);
	    loadrealvalue(opnd1);
	    end;
	  if eclass = subnode then
	    emit2(fsub,opnd2^.attr^,opnd1^.attr^)
	  else
	    emit2(fdiv,opnd2^.attr^,opnd1^.attr^);
	  freeregs(opnd2^.attr);
	  liftattr(fexp,opnd1);
	  end;
	addnode, mulnode: { 64 bit }
	  begin
	  { Evaluate a complicated operand first }
	  if opnd1^.num_ops >= opnd2^.num_ops then
	    begin
	    if opnd1^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd1^.opnd);
	      getattrec(opnd1);
	      liftattr(opnd1,opnd1^.opnd);
	      opnd1^.attr^.storage := opnd1^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd1);
	    if opnd2^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd2^.opnd);
	      getattrec(opnd2);
	      liftattr(opnd2,opnd2^.opnd);
	      opnd2^.attr^.storage := opnd2^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd2);
	    end
	  else
	    begin
	    if opnd2^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd2^.opnd);
	      getattrec(opnd2);
	      liftattr(opnd2,opnd2^.opnd);
	      opnd2^.attr^.storage := opnd2^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd2);
	    if opnd1^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd1^.opnd);
	      getattrec(opnd1);
	      liftattr(opnd1,opnd1^.opnd);
	      opnd1^.attr^.storage := opnd1^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd1);
	    end;
	  if opnd2^.attr^.addrmode = inFreg then
	    begin
	    if eclass = addnode then
	      emit2(fadd,opnd1^.attr^,opnd2^.attr^)
	    else
	      emit2(fmul,opnd1^.attr^,opnd2^.attr^);
	    freeregs(opnd1^.attr);
	    liftattr(fexp,opnd2);
	    end
	  else if opnd1^.attr^.addrmode = inFreg then
	    begin
	    if eclass = addnode then
	      emit2(fadd,opnd2^.attr^,opnd1^.attr^)
	    else
	      emit2(fmul,opnd2^.attr^,opnd1^.attr^);
	    freeregs(opnd2^.attr);
	    liftattr(fexp,opnd1);
	    end
	  else
	    begin
	    loadrealvalue(opnd2);
	    if eclass = addnode then
	      emit2(fadd,opnd1^.attr^,opnd2^.attr^)
	    else
	      emit2(fmul,opnd1^.attr^,opnd2^.attr^);
	    freeregs(opnd1^.attr);
	    liftattr(fexp,opnd2);
	    end;
	  end;
      end; { case eclass }
    end; { realop }
@


56.2
log
@
pws2rcs automatic delta on Wed Jan 27 11:57:27 MST 1993
@
text
@d1 400
@


56.1
log
@Automatic bump of revision number for PWS version 3.25
@
text
@a0 400
			     { file MC68881 }
import
  sysglobals, codegen, assemble, genutils, genexprmod;

implement

  var
    rmask,fregloc : attrtype;
    fregcount: shortint;

  procedure NIL_attributes(fexp: exptr);
    { Called as part of the $FLOAT TEST$ option }
    var
      ptr: elistptr;
    begin
    with fexp^ do
      begin
      attr := NIL;
      case eclass of
	eqnode, nenode, ltnode, lenode, gtnode, genode, innode, subsetnode,
	supersetnode, unionnode, diffnode, intersectnode, concatnode,
	addnode, subnode, mulnode, divnode, modnode, shftnode, ornode, andnode:
	  begin
	  NIL_attributes(opnd1);
	  NIL_attributes(opnd2);
	  end;
	negnode, notnode, floatnode, derfnode, succnode,
	bufnode, absnode, chrnode, oddnode, ordnode,
	prednode, strlennode, strmaxnode, roundnode, sqrnode, truncnode:
	  NIL_attributes(opnd);
	subscrnode:
	  begin
	  NIL_attributes(arayp);
	  NIL_attributes(indxp);
	  end;
	substrnode:
	  begin
	  NIL_attributes(arayp);
	  NIL_attributes(indxp);
	  NIL_attributes(lengthp);
	  end;
	selnnode:
	  NIL_attributes(recptr);
	fcallnode:
	  begin
	  ptr := actualp;
	  while ptr <> NIL do
	    begin
	    NIL_attributes(ptr^.expptr);
	    ptr := ptr^.nextptr;
	    end;
	  end;
	setdenonode:
	  begin
	  ptr := setvarpart;
	  while ptr <> NIL do
	    begin
	    NIL_attributes(ptr^.lowptr);
	    NIL_attributes(ptr^.hiptr);
	    ptr := ptr^.nextptr;
	    end;
	  end;
	otherwise { Terminal node }
      end; { case }
      end; { with }
    end; { NIL_attributes }


  procedure makerealaddressable( fexp : exptr );
	{ Make operand addressable while handling float node }
    begin
	  force_unpack := true;
	  makeaddressable(fexp);
	  force_unpack := false;
	  with fexp^.attr^ do
	    if ((storage = bytte) or (storage = wrd)) and not signbit then
	      extend(fexp,succ(storage));
    end;


  procedure loadrealvalue(fexp: exptr);
    { Load 64 bit real into a floating point register }
    var
      op : attrtype;
    begin
    makerealaddressable(fexp);
    if fexp^.attr^.addrmode <> inFreg then
      begin
      with op do
	begin
	regnum := getreg(F);
	addrmode := inFreg;
	storage := multi;
	end;
      with fexp^ do
	begin
	with attr^ do
	  if ((storage = bytte) or (storage = wrd)) and not signbit then
	    extend(fexp,succ(storage));
	freeregs(attr);
	emit2(fmove,attr^,op);
	attr^.storage := multi;
	attr^.addrmode := inFreg;
	attr^.regnum := op.regnum;
	end; { with fexp^ }
      end;
    end;

  procedure pushrealvalue(fexp: exptr);
    { Addrmode is inFreg.  Move the 64 bit
      real number onto the stack. }
    begin
    makerealaddressable(fexp);
    SPminus.storage := multi;
    emit2(fmove,fexp^.attr^,SPminus);
    freeregs(fexp^.attr);
    fexp^.attr^.addrmode := topofstack;
    end;

  procedure pushrealaddress(fexp: exptr);
    { Addrmode is inFreg. Move to a temporary.
      Push the address of the temporary.}
    var
      op: attrtype;
    begin
    makerealaddressable(fexp);
    getlocstorage(8,op);
    op.storage := multi;
    emit2(fmove,fexp^.attr^,op);
    emit1(pea,op);
    freeregs(fexp^.attr);
    end;

  procedure moverealvalue(fexp: exptr; var at: attrtype);
    { Addrmode is inFreg.  Move 64 bit real from
      the floating point registers to the address in at. }
    var
      op: attrtype;
    begin
    makerealaddressable(fexp);
    emit2(fmove,fexp^.attr^,at);
    freeregs(fexp^.attr);
    end;

  procedure saverealregs;
    var
      rn: regrange;

    begin
    with rmask do
      begin
      addrmode := fmultiple;
      fregcount := 0;
      for rn := 0 to maxreg do
	if reg[F,rn].allocstate = allocated then
	  begin
	  fregcount := fregcount + 1;
	  fregs[rn] := true;
	  end
	else
	  fregs[rn] := false;

      if fregcount > 0 then
	begin
	getlocstorage(fregcount*12,fregloc);
	emit2(fmovem,rmask,fregloc);  { Save registers in temporary storage }
	end;
      end;
    end;

  procedure reloadrealregs;

    begin
    if fregcount > 0 then
      emit2(fmovem,fregloc,rmask); { Restore registers from temporary storage }
    end;

  procedure realop(fexp: exptr);
    var
      op1,op2: attrtype;
      valp : csp;
    begin
    with fexp^, attr^ do
      case eclass of
	fcallnode:
	  with fptr^, actualp^ do
	    begin
	    if {actualp^.}expptr^.eclass = floatnode then
	      begin
	      makerealaddressable({actualp^.}expptr^.opnd);
	      getattrec({actualp^.}expptr);
	      liftattr({actualp^.}expptr,{actualp^.}expptr^.opnd);
	      {actualp^.}expptr^.attr^.storage :=
					{actualp^.}expptr^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable({actualp^.}expptr);
	    if spkey <> spln then
	      if {actualp^.}expptr^.attr^.addrmode = inFreg then
		with op1 do
		  begin
		  addrmode := inFreg;
		  regnum := {actualp^.}expptr^.attr^.regnum;
		  end
	      else
		begin
		freeregs({actualp^.}expptr^.attr);
		with op1 do
		  begin
		  addrmode := inFreg;
		  regnum := getreg(F);
		  end;
	      end;
	    case spkey of
	      spsin:    emit2(fsin,{actualp^.}expptr^.attr^,op1);
	      spcos:    emit2(fcos,{actualp^.}expptr^.attr^,op1);
	      spsqrt:   emit2(fsqrt,{actualp^.}expptr^.attr^,op1);
	      spexp:    emit2(fetox,{actualp^.}expptr^.attr^,op1);
	      sparctan: emit2(fatan,{actualp^.}expptr^.attr^,op1);
	      spln:
		begin
		loadrealvalue(expptr);
		new(valp);
		with valp^ do
		  begin
		  cclass := reel;
		  rval := 0.5;
		  end;
		with op1 do
		  begin
		  addrmode := labelledconst;
		  valp := poolit(valp);
		  constvalp := valp;
		  storage := multi;
		  offset := 0;
		  end;
		emit2(fcmp,op1,expptr^.attr^);
		op1.offset := 14;
		emit1(fblt,op1);
		with op1 do
		  begin
		  addrmode := immediate;
		  smallval := 1;
		  storage := wrd;
		  end;
		emit2(fsub,op1,expptr^.attr^);
		emit2(flognp1,expptr^.attr^,expptr^.attr^);
		op1.offset := 4;
		op1.storage := bytte;
		emit1(bra,op1);
		emit2(flogn,expptr^.attr^,expptr^.attr^);
		op1.regnum := expptr^.attr^.regnum;
		end;
	      end;
	    addrmode := inFreg;
	    regnum := op1.regnum;
	    storage := multi;
	    signbit := true;
	    end;
	negnode,absnode:   { 64 bit }
	  begin
	  makerealaddressable(opnd);
	  freeregs(opnd^.attr);
	  with op1 do
	    begin
	    addrmode := inFreg;
	    regnum := getreg(F);
	    end;
	  if eclass = negnode then
	    emit2(fneg,opnd^.attr^,op1)
	  else
	    emit2(fabs,opnd^.attr^,op1);
	  addrmode := inFreg;
	  regnum := op1.regnum;
	  storage := multi;
	  signbit := true;
	  end;
	sqrnode:
	  begin
	  loadrealvalue(opnd);
	  emit2(fmul,opnd^.attr^,opnd^.attr^);
	  liftattr(fexp,opnd);
	  end;
	floatnode: { int to 64 bit }
	  begin
	  loadrealvalue(opnd);
	  liftattr(fexp,opnd);
	  end;
	subnode, divnode: { 64 bit }
	  begin
	  { Evaluate a complicated operand first }
	  if opnd1^.num_ops >= opnd2^.num_ops then
	    begin
	    loadrealvalue(opnd1);
	    if opnd2^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd2^.opnd);
	      getattrec(opnd2);
	      liftattr(opnd2,opnd2^.opnd);
	      opnd2^.attr^.storage := opnd2^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd2);
	    end
	  else
	    begin
	    if opnd2^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd2^.opnd);
	      getattrec(opnd2);
	      liftattr(opnd2,opnd2^.opnd);
	      opnd2^.attr^.storage := opnd2^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd2);
	    loadrealvalue(opnd1);
	    end;
	  if eclass = subnode then
	    emit2(fsub,opnd2^.attr^,opnd1^.attr^)
	  else
	    emit2(fdiv,opnd2^.attr^,opnd1^.attr^);
	  freeregs(opnd2^.attr);
	  liftattr(fexp,opnd1);
	  end;
	addnode, mulnode: { 64 bit }
	  begin
	  { Evaluate a complicated operand first }
	  if opnd1^.num_ops >= opnd2^.num_ops then
	    begin
	    if opnd1^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd1^.opnd);
	      getattrec(opnd1);
	      liftattr(opnd1,opnd1^.opnd);
	      opnd1^.attr^.storage := opnd1^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd1);
	    if opnd2^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd2^.opnd);
	      getattrec(opnd2);
	      liftattr(opnd2,opnd2^.opnd);
	      opnd2^.attr^.storage := opnd2^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd2);
	    end
	  else
	    begin
	    if opnd2^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd2^.opnd);
	      getattrec(opnd2);
	      liftattr(opnd2,opnd2^.opnd);
	      opnd2^.attr^.storage := opnd2^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd2);
	    if opnd1^.eclass = floatnode then
	      begin
	      makerealaddressable(opnd1^.opnd);
	      getattrec(opnd1);
	      liftattr(opnd1,opnd1^.opnd);
	      opnd1^.attr^.storage := opnd1^.opnd^.attr^.storage;
	      end
	    else
	      makerealaddressable(opnd1);
	    end;
	  if opnd2^.attr^.addrmode = inFreg then
	    begin
	    if eclass = addnode then
	      emit2(fadd,opnd1^.attr^,opnd2^.attr^)
	    else
	      emit2(fmul,opnd1^.attr^,opnd2^.attr^);
	    freeregs(opnd1^.attr);
	    liftattr(fexp,opnd2);
	    end
	  else if opnd1^.attr^.addrmode = inFreg then
	    begin
	    if eclass = addnode then
	      emit2(fadd,opnd2^.attr^,opnd1^.attr^)
	    else
	      emit2(fmul,opnd2^.attr^,opnd1^.attr^);
	    freeregs(opnd2^.attr);
	    liftattr(fexp,opnd1);
	    end
	  else
	    begin
	    loadrealvalue(opnd2);
	    if eclass = addnode then
	      emit2(fadd,opnd1^.attr^,opnd2^.attr^)
	    else
	      emit2(fmul,opnd1^.attr^,opnd2^.attr^);
	    freeregs(opnd1^.attr);
	    liftattr(fexp,opnd2);
	    end;
	  end;
      end; { case eclass }
    end; { realop }
@


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@Automatic bump of revision number for PWS version 3.25A
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@Automatic bump of revision number for PWS version 3.24
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53.1
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@Automatic bump of revision number for PWS version 3.24B
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52.1
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@Automatic bump of revision number for PWS version 3.24A
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51.1
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@Automatic bump of revision number for PWS version 3.24d
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50.1
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@Automatic bump of revision number for PWS version 3.23c
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49.1
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@Automatic bump of revision number for PWS version 3.24b
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text
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48.1
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@Automatic bump of revision number for PWS version 3.24a
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47.1
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@Automatic bump of revision number for PWS version 3.23
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46.1
log
@Automatic bump of revision number for PWS version 3.23
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text
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45.1
log
@Automatic bump of revision number for PWS version 3.23C
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44.1
log
@Automatic bump of revision number for PWS version 3.23B
@
text
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43.1
log
@Automatic bump of revision number for PWS version 3.23aA
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42.1
log
@Automatic bump of revision number for PWS version 3.23e
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41.1
log
@Automatic bump of revision number for PWS version 3.23d
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text
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40.1
log
@Automatic bump of revision number for PWS version 3.23c
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text
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39.1
log
@Automatic bump of revision number for PWS version 3.23b
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38.1
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@Automatic bump of revision number for PWS version 3.23a
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text
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37.1
log
@Automatic bump of revision number for PWS version 3.3a
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text
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36.1
log
@Automatic bump of revision number for PWS version 3.22
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text
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35.1
log
@Automatic bump of revision number for PWS version 3.22
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text
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34.1
log
@Automatic bump of revision number for PWS version 3.22
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text
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33.1
log
@Automatic bump of revision number for PWS version 3.22D
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text
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32.1
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@Automatic bump of revision number for PWS version 3.22C
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text
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31.1
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@Automatic bump of revision number for PWS version 3.22B
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30.1
log
@Automatic bump of revision number for PWS version 3.22A
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text
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29.1
log
@Automatic bump of revision number for PWS version 3.22b
@
text
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28.1
log
@Automatic bump of revision number for PWS version 3.3b
@
text
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27.1
log
@Automatic bump of revision number for PWS version 3.3a
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text
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26.1
log
@Automatic bump of revision number for PWS version 3.3 Synch
@
text
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25.1
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@Automatic bump of revision number for PWS version 3.2Y
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text
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24.1
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@Automatic bump of revision number for PWS version 3.2
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text
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23.1
log
@Automatic bump of revision number for PWS version 3.2P
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text
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22.1
log
@Automatic bump of revision number for PWS version 3.2N
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text
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21.1
log
@Automatic bump of revision number for PWS version 3.2M
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text
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20.1
log
@Automatic bump of revision number for PWS version 3.2L
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text
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19.1
log
@Automatic bump of revision number for PWS version 3.2K
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text
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18.1
log
@Automatic bump of revision number for PWS version 3.2J
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17.1
log
@Automatic bump of revision number for PWS version 3.2I+
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16.1
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@Automatic bump of revision number for PWS version 3.2I
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15.1
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@Automatic bump of revision number for PWS version 3.2H
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14.1
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@Automatic bump of revision number for PWS version 3.2G
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13.1
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@Automatic bump of revision number for PWS version 3.2F
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12.1
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@Automatic bump of revision number for PWS version 3.2E
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11.1
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@Automatic bump of revision number for PWS version 3.2D
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10.1
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@Automatic bump of revision number for PWS version 3.2C
@
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9.2
log
@Fix for character - > real conversion in COMPILE20
@
text
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9.1
log
@Automatic bump of revision number for PWS version 3.2B
@
text
@d75 3
d97 3
@


8.1
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@Automatic bump of revision number for PWS version 3.2A
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7.1
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@Automatic bump of revision number for PWS version 3.2l
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@Automatic bump of revision number for PWS version 3.2k
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5.1
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@Automatic bump of revision number for PWS version 3.2j
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4.1
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@Automatic bump of revision number for PWS version 3.2i
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3.2
log
@Changes from Scott Bayes.
@
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3.1
log
@Automatic bump of revision number for PWS version 3.2h
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text
@d68 10
d83 1
a83 1
    makeaddressable(fexp);
d107 1
a107 1
    makeaddressable(fexp);
d120 1
a120 1
    makeaddressable(fexp);
d134 1
a134 1
    makeaddressable(fexp);
d184 1
a184 1
	      makeaddressable({actualp^.}expptr^.opnd);
d191 1
a191 1
	      makeaddressable({actualp^.}expptr);
d256 1
a256 1
	  makeaddressable(opnd);
d291 1
a291 1
	      makeaddressable(opnd2^.opnd);
d297 1
a297 1
	      makeaddressable(opnd2);
d303 1
a303 1
	      makeaddressable(opnd2^.opnd);
d309 1
a309 1
	      makeaddressable(opnd2);
d326 1
a326 1
	      makeaddressable(opnd1^.opnd);
d332 1
a332 1
	      makeaddressable(opnd1);
d335 1
a335 1
	      makeaddressable(opnd2^.opnd);
d341 1
a341 1
	      makeaddressable(opnd2);
d347 1
a347 1
	      makeaddressable(opnd2^.opnd);
d353 1
a353 1
	      makeaddressable(opnd2);
d356 1
a356 1
	      makeaddressable(opnd1^.opnd);
d362 1
a362 1
	      makeaddressable(opnd1);
@


2.1
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@Auto bump rev number to 2.1 for sys 3.2e.
@
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1.1
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@Initial revision
@
text
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