; $NetBSD$

;
; Copyright (c) 1994 Mark Brinicombe.
; Copyright (c) 1994 Brini.
; All rights reserved.
;
; This code is derived from software written for Brini by Mark Brinicombe
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; 1. Redistributions of source code must retain the above copyright
;    notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
;    notice, this list of conditions and the following disclaimer in the
;    documentation and/or other materials provided with the distribution.
; 3. All advertising materials mentioning features or use of this software
;    must display the following acknowledgement:
;	This product includes software developed by Brini.
; 4. The name of the company nor the name of the author may be used to
;    endorse or promote products derived from this software without specific
;    prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
; WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
; IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
; SUCH DAMAGE.
;
; RiscBSD kernel project
;
; svc32.s
;
;
;
; Created      : 12/09/94
; Last updated : 12/09/94
;
; Based on kate/library/svc32.s
;
;    $Id$
;

	GET	h.asmregs
	GET	h.arm6

        AREA |C$$code|, CODE, READONLY

        EXPORT SVC32

; Switches from SVC26 mode to SVC32 mode
;
SVC32
        mrs     a2, CPSR_all
;	mrs	AL, a2, CPSR_all
	BIC	a2, a2, #2_11111
	ORR	a2, a2, #SVC32_mode
	msr	CPSR_all, a2
;        msr     AL, CPSR_all, a2

	BIC	lr, lr, #&fc000000

	MOV	pc, lr

        END
