
			/*
			 * Format all of the FPU data registers.
			 */
			for (i=0; i <= 7; i++) {
				register u_long * lp = &u.u_FPDR[0];

				if (i == 4)	printf("\n");
				printf("    FPDR[%d]: %08x %08x %08x\",
					i, *lp, *(lp+1), *(lp+2));
			}

			/*
			 * Format the FPU CONTROL Register.
			 */
			printf("\nu_FPCR @ 0x%x, size=0x%x, =0x%8x",
			     &u.u_FPCR, sizeof(u.u_FPCR), u.u_FPCR);


			/*
			 * Format the FPU STATUS Register.
			 */
			printf("u_FPSR @ 0x%x, size=0x%x, =0x%x ",
			     &u.u_FPSR, sizeof(u.u_FPSR), u.u_FPSR);
			/*
			 * ...Condition Code Byte...
			 */
			printf(" ==> CC==%s,%s,%s,%s\n",
				(u_FPCR & FPU_N_CCODE)	? "Negative"	: "",
				(u_FPCR & FPU_Z_CCODE)	? "Zero"	: "",
				(u_FPCR & FPU_I_CCODE)	? "Infinity"	: "",
				(u_FPCR & FPU_NAN_CCODE)? "NotANumber"	: ""
			      );
			/*
			 * ...Exception Status Byte...
			 */
			printf(" ==> ES==%s,%s,%s,%s| %s,%s,%s,%s\n",
			  (u_FPCR & FPU_BSUN_STAT)	? "BSUN"	: "",
			  (u_FPCR & FPU_SNAN_STAT)	? "SNAN"	: "",
			  (u_FPCR & FPU_OPERR_STAT)	? "OperandErr"	: "",
			  (u_FPCR & FPU_OVFL_STAT)	? "Overflow"	: "",

			  (u_FPCR & FPU_UNFL_STAT)	? "Underflow"	: "",
			  (u_FPCR & FPU_DZ_STAT)	? "DivByZero"	: "",
			  (u_FPCR & FPU_INEX2_STAT)	? "InexactOp"	: "",
			  (u_FPCR & FPU_INEX1_STAT)	? "InexactDecIn": ""
			      );
			/*
			 * ...Accrued Exception Byte...
			 */
			printf(" ==> AE==%s,%s,%s,%s| %s\n",
			  (u_FPCR & FPU_IOP_EXCPT)	? "Invalid-Op "	: "",
			  (u_FPCR & FPU_OVFL_EXCPT)	? "Overflow "	: "",
			  (u_FPCR & FPU_UNFL_EXCPT)	? "Underflow "	: "",
			  (u_FPCR & FPU_DZ_EXCPT)	? "DivByZero "	: "",

			  (u_FPCR & FPU_INEX_EXCPT)	? "Inexact "	: ""
			      );


